MediaTek Announces Helio X30 Availability: 10 CPU Cores On 10nm

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• andrewaggb - Tuesday, February 28, 2017 - link

  I wish they'd give some real-world examples comparing their design to some competitors. Logically I get it, A35's for idle/low load (low power, low clocks), A53's (mid power, mid clocks), and A73's for high performance.
  
  But there are only 2 A73's and 4 A53's and 4 A35's. You'd think you should have 4 A73's and are there scenarios where 4 A53's may match or exceed? Can you run the A73's with the A53's?
  Why not just 4 A35's and 4 A73's? What is the cluster switching penalty? Are cache lines and everything the same or will some software need to be recompiled or be aware of these changes.
  
  Anyways it's interesting and sounds pretty good, just wish we had more information. It's also interesting because intel and AMD haven't used this approach (atom cores + core) or (jaguar + bulldozer) and instead have favored dynamically adjusting clock speeds across a wide range.

• Matt Humrick - Tuesday, February 28, 2017 - link

  It's a tradeoff between performance and power/area. The cost of adding additional big cores is not negligible. All 3 clusters (or 2 in conventional big.little) can be online at the same time. The latency penalty for hotplugging cores and migrating threads between clusters is more than offset by the additional performance of the big cores (or lower power going the other way). The use of a high-bandwidth, cache-coherent (at the hardware level) interconnect reduces the migration penalty.

• abufrejoval - Tuesday, February 28, 2017 - link

  I keep hearing that at least the small cores are really tiny in terms of surface area. I remember overall 15% for all CPU cores, BIG and little on the SoC and that was a couple of generations back. Within those 15% the big A73 core may relatively large in terms of surface area, not only for the far more complex OoO logic etc. but because they require big caches for effective work. Then adding one, two or four small cores may add single digit surface percentage, because last level caches remain shared, primary caches are tiny and less needed at the slow speeds but most importantly allow more GPU block connections to keep those busy for "perceived" speed on scrolls, video etc., whilst the big cores are sleeping.
  
  In addition those extra CPU cores won't cost much in terms of ARM licensing fees, because the biggest charge is on the number of the BIG cores, the smaller ones seem to be thrown in to the bundle.
  
  Silicon real-estate and licensing fee economicy should perhaps get more editorial space to lessen these confusions, but few vendors seem willing to talk about them.

• serendip - Wednesday, March 1, 2017 - link

  What the mobile segment really needs isn't a bunch of barely differentiated CPU cores, it needs a freaking ton of small GPU cores that support programming a la CUDA or OpenCL. I'm already happy with a 4x little and 2x big core setup. Having access to hundreds of programmable simple cores would be great for custom image processing, neural networks, sound processing etc. as long as those cores are easily accessible. DSPs hidden behind proprietary blobs like Qualcomm's Hexagon don't count.

• Meteor2 - Tuesday, March 14, 2017 - link

  Tegra X1.

• extide - Sunday, May 7, 2017 - link

  FWIW, to give an example a single A72/73 core is bigger than an entire quad core cluster of A35/53 cores. It's cheaper (in terms of transistor budget or die size) to add a whole cluster of A53's than to add even a single extra A72/73, so to add two more is quite a bit different. I bet thats a large reason MTK is pushing these cores, 10>8 = great for marketing and less die space is great for the bottom line...

• nandnandnand - Wednesday, December 1, 2021 - link

  I'm from the future! Intel and AMD are using this approach!