TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it has over a dozen of customers with tens of designs eager to use the technology to make their integrated circuits.

The 7 nm node is a big deal for the foundry industry in general and TSMC in particular. When compared to the CLN16FF+ technology (TSMC’s most widely used FinFET process technology) the CLN7FF will enable chip designers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60%, or increase frequency by 30% (at the same complexity). So far, TSMC has taped out 18 customer products using the CLN7FF technology, more than 50 CLN7FF products will be taped out by the end of 2018.

Unlike TSMC’s CLN10FF, which is used by a limited number of customers for a limited number of mobile SoCs, the CLN7FF is expected to be used to build CPUs, GPUs, FPGAs, neural network processors, cryptocurrency mining accelerators, mobile SoCs and so on. This is important because demand for smartphones is slowing down and TSMC needs other customers to offset lower orders for mobile SoCs.

“So far, we have already favored out more than 18 customer products with good yield [and] performance,” said C. C. Wei, a Co-CEO and President of TSMC, during a conference call with financial analysts. “More than 50 products tape-outs has been planned by end of this year from applications across mobile, server CPU, network processor, gaming, GPU, PGA, cryptocurrency, automotive and AI. Our 7nm is already in volume production.”

TSMC’s CLN7FF process technology will rely on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. As a result, the world’s largest contract maker of semiconductors will be able to use existing manufacturing tools to make 7 nm chips. Meanwhile, to keep using DUV lithography the company and its customers have to use multipatterning (triple and quadruple patterning), which increases design and production costs as well as product cycles.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  TSMC
16FF+
vs
20SOC
10FF
vs
16FF+
7FF
vs
16FF+
7FF
vs
10FF
7FF+
vs
7FF
Power 60% 40% 60% <40% 10%
Performance 40% 20% 30% ? higher
Area Reduction none >50% 70% >37% ~17%

Next year TSMC intends to introduce its first manufacturing tech that will use extreme ultraviolet lithography (EUVL) for select layers. The CLN7FF+ will be the company’s second-generation 7 nm fabrication process because of maximized design rules compatibility and because it will keep using DUV tools that TSMC uses today for its CLN7FF production. From a general PPA (power, performance, area) improvement point of view, TSMC expects its CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. Furthermore, TSMC’s EUV-based 7 nm technology could also feature higher performance and a tighter distribution of currents, but the company’s execs do not quantitate the improvements just now.

“Our N7+ silicon result today are very encouraging,” said Mr. Wei. “Not only we have demonstrated equivalent or better performance [and] yield on both 256 Mb SRAM and on product like test vehicle when compared to [the] N7 baseline, we have also demonstrated a tighter distribution of electrical parameters in the areas, where EUV is supplied.”

TSMC is on track to start HVM using its 7 nm EUV process technology in mid-2019. Going forward, the company will increase usage of ASML’s Twinscan NXE step and scan systems when it starts to process wafers using its CLN5 (5 nm) process technology in 2020. According to the co-CEO of TSMC, the EUV results have been encouraging so far: the company’s 256 Mb SRAM test chip is already made with a “consistent double-digit yield”, which is rather good for a technology that is two years away from HVM. The high-ranking executive of TSMC also noted that the EUV infrastructure in general has made a good progress in the recent quarters. In particular, the company observed lower pellicle defects, higher mask yields, and improved photoresists. 

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  • levizx - Sunday, May 13, 2018 - link

    No, GF hasn't had an in-house SOI process for a long time now. 14 FF+SOI was from IBM and will only be used on POWER9. It's 22FDX hasn't reached production stage yet and is not for general purpose chips. Reply
  • James5mith - Wednesday, April 25, 2018 - link

    Memory manufacturers aren't worried about cost sensitivity right now. With the artificial price inflation over the last 1-2 years, they have padding in their bottom line. Reply
  • xidex2 - Wednesday, April 25, 2018 - link

    It has been rumored that AMD will actually use GF for its GPU stack and TSMC for Zen 2 and so on. Reply
  • ZolaIII - Wednesday, April 25, 2018 - link

    The SRAM cells are used for testing new nodes because of their structural simplicity which also lowers the error rate & they future improve the node on it before going in with more complex structures, multi structures... Second phase is smaller complex SoC's then mid size ones & last one is huge GPU's or FPGA's. Think we will see first consumer products by the beginning of the next year certainly from Samsung and Qualcomm and probably from Apple, rest of mobile will kick in in the second half of the year & first GPU's & FPGA's only in 2020. Reply
  • bcronce - Wednesday, April 25, 2018 - link

    You can't just use smaller transistors for general memory. DDR4 is 1v-1.4v. 7nm transistors operate around 0.7v. You'd need resistors to drop the voltage to make 7nm work with DDR4. Reply
  • eSyr - Tuesday, April 24, 2018 - link

    Apple A12? Reply
  • name99 - Tuesday, April 24, 2018 - link

    Or Apple A11X... That's a tricky one because there's no definite schedule for it.

    One possibility is that it was scheduled for this sort of time (Q2), to be fabbed on 7FF, and TSMC slipped by a quarter. So we will see new iPads with A11X Q3 (maybe announced at WWDC?)

    Another possibility (with all the Spectre/Meltdown stuff) is that Apple decided to treat it as a sacrificial chip --- make various tests to it to see what was safe and could easily be retrofitted to defeat Spectre/Meltdown --- so that those could be added to A12 in time. Meaning a "research" chip with a bunch of weird mods, that can't be sold to end-users. Expensive!
    But maybe they decided, all things considered and looking at the big picture [which includes getting to desktop CPUs by 2020] it was the best option?

    Or perhaps no A11X? Maybe Apple figures iPads are good enough right now, and so all effort is going into A12X (to be their first chip on EUV 7FF+)? Maybe the iPad cadence going forward is to expect new SoCs every two years, not every year?
    Reply
  • ZolaIII - Wednesday, April 25, 2018 - link

    If Apple survives at all in the mean time which won't happen if China bans them which they should. When things start to go down hill the biggest cuts are in R&D department. Reply
  • Speedfriend - Wednesday, April 25, 2018 - link

    I read an analyst piece recently saying that Apple is using 7nm for both 2018 and 2019, not 7nm+ in 2019 as they are wanting to manufacture early in the year now. Reply
  • ZolaIII - Wednesday, April 25, 2018 - link

    Well you read now how 7nm TSMC is getting ready only now for a mass production meaning in the best bet they will need additional 3 more months to improve yields so that is in uper part of two digits for medium sized SoC's and Apple needs at least 3 more to manufacture them in significant enough amount which makes it on time for traditional holiday season launch, but that's still a best case scenario. Samsung will certainly be ready on spring season with both Exynos and Snapdragon products. Reply

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