TSMC last week announced that it had started high volume production (HVM) of chips using their first-gen 7 nm (CLN7FF) process technology. The contract maker of semiconductors says it has over a dozen of customers with tens of designs eager to use the technology to make their integrated circuits.

The 7 nm node is a big deal for the foundry industry in general and TSMC in particular. When compared to the CLN16FF+ technology (TSMC’s most widely used FinFET process technology) the CLN7FF will enable chip designers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60%, or increase frequency by 30% (at the same complexity). So far, TSMC has taped out 18 customer products using the CLN7FF technology, more than 50 CLN7FF products will be taped out by the end of 2018.

Unlike TSMC’s CLN10FF, which is used by a limited number of customers for a limited number of mobile SoCs, the CLN7FF is expected to be used to build CPUs, GPUs, FPGAs, neural network processors, cryptocurrency mining accelerators, mobile SoCs and so on. This is important because demand for smartphones is slowing down and TSMC needs other customers to offset lower orders for mobile SoCs.

“So far, we have already favored out more than 18 customer products with good yield [and] performance,” said C. C. Wei, a Co-CEO and President of TSMC, during a conference call with financial analysts. “More than 50 products tape-outs has been planned by end of this year from applications across mobile, server CPU, network processor, gaming, GPU, PGA, cryptocurrency, automotive and AI. Our 7nm is already in volume production.”

TSMC’s CLN7FF process technology will rely on deep ultraviolet (DUV) lithography with argon fluoride (ArF) excimer lasers operating on a 193 nm wavelength. As a result, the world’s largest contract maker of semiconductors will be able to use existing manufacturing tools to make 7 nm chips. Meanwhile, to keep using DUV lithography the company and its customers have to use multipatterning (triple and quadruple patterning), which increases design and production costs as well as product cycles.

Advertised PPA Improvements of New Process Technologies
Data announced by companies during conference calls, press briefings and in press releases
  TSMC
16FF+
vs
20SOC
10FF
vs
16FF+
7FF
vs
16FF+
7FF
vs
10FF
7FF+
vs
7FF
Power 60% 40% 60% <40% 10%
Performance 40% 20% 30% ? higher
Area Reduction none >50% 70% >37% ~17%

Next year TSMC intends to introduce its first manufacturing tech that will use extreme ultraviolet lithography (EUVL) for select layers. The CLN7FF+ will be the company’s second-generation 7 nm fabrication process because of maximized design rules compatibility and because it will keep using DUV tools that TSMC uses today for its CLN7FF production. From a general PPA (power, performance, area) improvement point of view, TSMC expects its CLN7FF+ to offer a 20% higher transistor density and a 10% lower power consumption at the same complexity and frequency when compared to the CLN7FF. Furthermore, TSMC’s EUV-based 7 nm technology could also feature higher performance and a tighter distribution of currents, but the company’s execs do not quantitate the improvements just now.

“Our N7+ silicon result today are very encouraging,” said Mr. Wei. “Not only we have demonstrated equivalent or better performance [and] yield on both 256 Mb SRAM and on product like test vehicle when compared to [the] N7 baseline, we have also demonstrated a tighter distribution of electrical parameters in the areas, where EUV is supplied.”

TSMC is on track to start HVM using its 7 nm EUV process technology in mid-2019. Going forward, the company will increase usage of ASML’s Twinscan NXE step and scan systems when it starts to process wafers using its CLN5 (5 nm) process technology in 2020. According to the co-CEO of TSMC, the EUV results have been encouraging so far: the company’s 256 Mb SRAM test chip is already made with a “consistent double-digit yield”, which is rather good for a technology that is two years away from HVM. The high-ranking executive of TSMC also noted that the EUV infrastructure in general has made a good progress in the recent quarters. In particular, the company observed lower pellicle defects, higher mask yields, and improved photoresists. 

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  • jjj - Wednesday, April 25, 2018 - link

    All the relevant metrics come together to determine where the customer goes and nobody votes for Intel with their wallet today. It's as simple as that and all else is BS. Reply
  • ZolaIII - Wednesday, April 25, 2018 - link

    The TSMC 12nm is renamed 16nm FinFET, it's not faster than second generation of their second generation 16nm that's made for performance. Utilised rooting libs on 12nm one are 17% denser it's also simplified as it has less layers & this makes it more cost efficient, which translates to 10% more power efficient while being 6~7% slower but you use that 10% power headroom to bump clock's up & anullate performance difference & still have 20~25% cheaper production (size difference combined with less layers). Re introduction of the SOI wafers on FinFET structure from GF will not be a game changer but it will certainly be a turning point defeating Intel in it's own game of high performance node's as 7nm from GF will be denser than Intels 10nm while SOI wafer will bring huge leaking important which will be much more ahead of Intels better fin structural form. I am talking of 20~30% performance difference or 30~50% density difference so 20~25% cheaper chip that performs 20% better & costs 20% less (more tied to CPUs) or same sized one that costs the same & performs 30~35% better (more tied for high parallel structures; GPU's, FPGA's, DSP's). Reply
  • FullmetalTitan - Wednesday, April 25, 2018 - link

    Intel has a higher aspect ratio FINFET, which allows for higher performance, at the cost of some efficiency (leakage/heat generation). But just looking at density, Samsung and TSMC passed up Intel's current offerings when they started shipping their respective 10nm products.

    Intel 10nm has been delayed for YEARS, and will be on roughly the same density tier as TSMC/Samsung 7nm.
    Reply
  • haukionkannel - Wednesday, April 25, 2018 - link

    Well not yet because They allready have 10nm production. Just not commercial products yet. And Intel 10nm is same or Little bit smaller than thin 7nm... but it is possible that They will lose it if commercial products come out with this 7nm before Intel own 10nm is on the shops. Reply
  • sgeocla - Wednesday, April 25, 2018 - link

    The best estimate Intel has about it's 10nm is that it is x% of the competitor's 7nm. They probably would have used 'better' or some other adjective if their 10nm was actually ahead. Reply
  • Wilco1 - Wednesday, April 25, 2018 - link

    Intel 10nm isn't in high volume production. If it was we would know about it given all the delays.

    Note TSMC 7nm is more dense than Intel 10nm just like TSMC 10nm is more dense than Intel 14nm.
    Reply
  • edzieba - Wednesday, April 25, 2018 - link

    We know Intel has already shipped 10nm parts (https://www.anandtech.com/show/12271/intel-mention... , https://www.anandtech.com/show/12436/intel-10nm-du... The GPU-less dies seems a good fit for the upcoming Crimson Canyon NUCs (and likely the same package uses in Mac Minis/Macbooks/etc) with a lower power CPU + GPU combo than Kaby Lake G. Reply
  • Wilco1 - Wednesday, April 25, 2018 - link

    It's standard practice to ship test chips to customers - not the same as volume production. Reply
  • ZolaIII - Wednesday, April 25, 2018 - link

    It lost the process lead in the second half of last year & it lost the quantity lead at the end of last year. Samsung is now largest semiconductor manufacturer with whooping portfolio of products and IP's including third part licensable one's. Samsung retained flexibility & did some clever planing ahead of time so that it can get high profit margins & utilities it's capacities best way possible (last year it whose NAND production now it's SRAM [SDDR, HMB]). Those are two things Intel never had, only X86 monopoly & that space is shrinking for them. Reply
  • Scabies - Tuesday, April 24, 2018 - link

    >cryptocurrency mining accelerators

    This is my first time seeing this term.
    I dont like it.
    Reply

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