The Intel Lakefield Deep Dive: Everything To Know About the First x86 Hybrid CPU
by Dr. Ian Cutress on July 2, 2020 9:00 AM ESTThermal Management on Stacked Silicon
With a standard processor design, there is a single piece of silicon doing all the work and generating the heat – it’s bonded to the package (which doesn’t do any work) and then depending on the implementation, there’s some adhesive to either a cooler or a headspreader then a cooler. When moving to a stacked chiplet design, it gets a bit more complicated.
Having two bits of silicon that ‘do work’, even if one is the heavy compute die and the other is an active interposer taking care of USB and audio and things, does mean that there’s a thermal gradient between the silicon, and depending on the bonding, potential for thermal hotspots and build-up. Lakefield makes it even more complex, by having an additional DRAM package placed on top but not directly bonded.
We can take each of these issues independently. For the case of die-on-die interaction, there is a lot of research going into this area. Discussions and development about fluidic channels between two hot silicon dies have been going on for a decade or longer in academia, and Intel has mentioned it a number of times, especially when relating to a potential solution of its new die-to-die stacking technology.
They key here is hot dies, with thermal hotspots. As with a standard silicon design, ideally it is best to keep two high-powered areas separate, as it gives a number of benefits with power delivery, cooling, and signal integrity. With a stacked die, it is best to not have hotspots directly on top of each other, for similar reasons. Despite Intel using its leading edge 10+ process node for the compute die, the base die is using 22FFL, which is Intel’s low power implementation of its 14nm process. Not only that, but the base die is only dealing with IO, such as USB and PCIe 3.0, which is essentially fixed bandwidth and energy costs. What we have here is a high-powered die on top of a low powered die, and as such thermal issues between the two silicon die, especially in a low TDP device like Lakefield (7W TDP), are not an issue.
What is an issue is how the compute die gets rid of the heat. On the bottom it can do convection by being bonded to more silicon, but the top is ultimately blocked by that DRAM die. As you can see in the image above, there’s a big air gap between the two.
As part of the Lakefield design, Intel had to add in a number of design changes in order to make the thermals work. A lot of work can be done with the silicon design itself, such as matching up hotspots in the right area, using suitable thickness of metals in various layers, and rearranging the floorplan to reduce localized power density. Ultimately both increasing the thermal mass and the potential dissipation becomes high priorities.
Lakefield CPUs have a sustained power limit of 7 watts – this is defined in the specifications. Intel also has another limit, known as the turbo power limit. At Intel’s Architecture Day, the company stated that the turbo power limit was 27 watts, however in the recent product briefing, we were told is set at 9.5 W. Historically Intel will let its OEM partners (Samsung, Lenovo, Microsoft) choose its own values for these based on how well the design implements its cooling – passive vs active and heatsink mass and things like this. Intel also has another factor of turbo time, essentially a measure of how long the turbo power can be sustained for.
When we initially asked Intel for this value, they refused to tell us, stating that it is proprietary information. After I asked again after a group call on the product, I got the same answer, despite the fact that I informed the Lakefield team that Intel has historically given this information out. Later on, I found out through my European peers that in a separate briefing, they gave the value of 28 seconds, to which Intel emailed me this several hours afterwards. This value can also be set by OEMs.
Then I subsequently found one of Intel’s ISSCC slides.
This slide shows that a basic implementation would only allow sustained power for 2.5 seconds. Adding in an adhesive between the top die and the DRAM moves up to 12.4 seconds, and then improving the system cooling goes up to 20 seconds. The rest of the improvements work below the compute die: a sizeable improvement comes from increasing the die-to-die metal density, and then an optimized power floor plan which in total gives sustained power support for 150+ seconds.
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yeeeeman - Friday, July 3, 2020 - link
The successor (Gracemont) comes next year in Alder Lake S. Stop being a hater and go eat your amd cake.anonomouse - Thursday, July 2, 2020 - link
There are bigger challenges for asymmetric core design beyond just the actual ISA support and scheduling, too. Multithreaded software has lots of assumptions around locks and spinlocks in particular that will have to be tuned, and effective priority inversions will be problematic too. Like where a thread on the big core has to wait on a lock that is held by a thread running on a small core.Notebookcheck's article made it seem like the scheduling right now just doesn't sustain using all of the Tremonts + the Sunny Cove at the same time, which neatly sort of sidesteps the issue for now, at obvious cost of the perf of that bigger core. Not clear whether that's intended behavior that will stick around.
wr3zzz - Thursday, July 2, 2020 - link
There is no need for so many little cores if software were not designed to continuously phone home with our personal data, or skimming money continuously via micro-transactions. The entire ecosystem of phones is designed around that concept. PC, not so much, for now.jeremyshaw - Thursday, July 2, 2020 - link
Too late. MSFT and Intel are pushing that rehashed garbage "Modern Standby" (formerly Connected Standby, InstantGo, etc), which is trying to make laptops that don't go into standby - rather they go into a low idle state and "perform tasks" throughout the night.Usually, it just drains the battery on my laptop (I have long disabled automatic mail retrieval, and any other scheduled task) and forces the laptop into hibernate. Just what I want out of my laptop - less battery life.
Luckily for us, AMD laptops don't support this garbage fire.
MSFT... just because Apple was able to successfully implement "Modern Standby" almost a decade ago, doesn't mean you can. Wake up. Or not.
abufrejoval - Friday, July 3, 2020 - link
Yeah, had to laptop batteries killed because they woke up in the middle of a flight packed tight and overheating. Hybrid and modern standby are absolute "killer features".brantron - Thursday, July 2, 2020 - link
Why not two tiny Cannon Lake cores?I'm no Intel engineer, but the inconvenient fact remains that such a device would be more useful to the average person.
That leaves Lakefield with the appearance of a frankenstein experiment. Sorry Intel, sounds fun, but I don't buy those for $1,000+.
serendip - Thursday, July 2, 2020 - link
This is the most damning quote from the article:"Intel has made the 1+4 design to act as a 0+4 design that sometimes has access to a higher performance mode. Whereas smartphone chips are designed for all eight cores to power on for sustained periods, Lakefield is built only for 0+4 sustained workloads. And that might ultimately be its downfall."
And this is going into $1000 devices like the Galaxy Book S and Thinkpad Fold. The ARM 8cx variant of the Galaxy Book S is $999, the Surface Pro X with an upgraded 8cx is also $999, and these offer i5 level performance when running ARM code. They also have surprisingly beefy integrated GPUs.
Now imagine paying $999 for a 4-core Atom device with a Sunny Cove core that mostly sits idle. I've used cheap Bay Trail and Apollo Lake Atoms, they're decent performers at low price points but they don't belong in anything over $500 because they're still laggy.
I've also compared the Pentium 4415Y vs. the m3-8100Y in the old and new Surface Go: the Kaby Lake Pentium dual-core feels slightly laggy because it can't turbo, whereas the m3 feels much more snappy when it turbos. Even then, the Pentium still feels more snappy than Apollo Lake because single-core performance is higher. For daily use, Windows likes fat beefy cores with high turbo because a lot of the UI is single-threaded.
brantron - Friday, July 3, 2020 - link
And in addition to the m3's turbo, there's hyper-threading and AVX to account for.What clock speed would Ice Lake Y or Tiger Lake Y have with no hyper-threading or AVX?
Something doesn't add up here, and it's not just the bizarre hybrid cores.
serendip - Friday, July 3, 2020 - link
Yes, the m3 has HT and so does the much maligned Pentium Gold 4415Y and 4425Y.Lakefield looks fascinating from purely technical viewpoint but from a value standpoint, it looks to be a disaster. Intel actually thinks 4 Tremont Atom cores are going to be the main cores for $1000 devices.
Meteor2 - Friday, July 3, 2020 - link
Think of the margins though