‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5
by Dr. Ian Cutress on August 25, 2020 9:30 AM EST
One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.
The measure used for defect density is the number of defects per square centimeter. Anything below 0.5/cm2 is usually a good metric, and we’ve seen TSMC pull some really interesting numbers, such as 0.09 defects per square centimetre on its N7 process node only three quarters after high volume manufacturing started, as was announced in November at the VLSI Symposium 2019. As it stands, the defect rate of a new process node is often compared to what the defect rate was for the previous node at the same time in development. As a result, we got this graph from TSMC’s Technology Symposium this week:
As it stands, the current N5 process from TSMC has a lower defect density than N7 did at the same time in its development cycle. TSMC. This slide from TSMC was showcased near the start of the event, and a more detailed graph was given later in the day:
This plot is linear, rather than the logarithmic curve of the first plot. This means that TSMC’s N5 process currently sits around 0.10 to 0.11 defects per square centimeter, and the company expects to go below 0.10 as high volume manufacturing ramps into next quarter.
Part of what makes 5nm yield slightly better is perhaps down to the increasing use of Extreme UltraViolet (EUV) technology, which reduces the total number of manufacturing steps. Each step is a potential chance to decrease yield, so by replacing 4 steps of DUV for 1 step of EUV, it eliminates some of that defect rate.
TSMC’s first 5nm process, called N5, is currently in high volume production. The first products built on N5 are expected to be smartphone processors for handsets due later this year.
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- Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020
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melgross - Tuesday, August 25, 2020 - link
Not CPUs.lmcd - Tuesday, August 25, 2020 - link
Gonna be honest I did not expect this. Intel is actually screwed :-/webdoctors - Tuesday, August 25, 2020 - link
Maybe this means the pricing on the N5 won't be insane. It'll be nice if its comparable to N7 but probably won't be for 5 yrs....nevertheless great work!vladx - Tuesday, August 25, 2020 - link
Wafer capacity is sold in Dutch auction style so the price is set by the clients.TimSyd - Tuesday, August 25, 2020 - link
The article & graphs show a timeline more like 5qtrs not 5yrsd. Where on earth did you get that idea?N5 *will* be expensive. Lots of EUV isn't cheap & throughput will be lower that they'd like. Both mean more $$ per wafer. I expect north of $15k/wafer easily though maybe volume/favoured customer discounts will pull that down below $12k/wafer mark.
TomWomack - Tuesday, August 25, 2020 - link
This is absolutely fascinating; defect-density curves with numbers on them are I think actually unprecedented (iirc Intel once provided a handout with numbers on but all the reporting of it was very quickly taken down). And that a mature process sticks at 0.1 defect per square centimetre (IE about 40% fully functioning 800mm^2 chips) for a year surprises me a lot, but possibly TSMC has finitely many fab engineers and would prefer to use them on getting the defect densities for newer processes down to a level they consider liveable with.Wilco1 - Wednesday, August 26, 2020 - link
According to https://caly-technologies.com/die-yield-calculator... it's actually 47% for 800mm^2! And many of the failed dies may be salvageable since large dies have a lot of redundancy.Spunjji - Thursday, August 27, 2020 - link
Yeah, 47% perfect dies for a chip of that size is absolute gangbusters. At that rate you're not even getting a clear majority of second-tier usable chips from each wafer, which is an interesting problem to have.Kamus - Tuesday, August 25, 2020 - link
Holy crap... these guys are on fire. Who ever made the choice at nVidia to go with Samsung instead of TSMC for Ampere should be fired, re-hired, and fired again.vladx - Tuesday, August 25, 2020 - link
Nvidia's architecture is so far ahead of the game that they just don't need the best fab process, they can use a lesser one and still kick AMD's and Intel's asses with ease.