Tenstorrent this week announced that it had signed a deal to license out its RISC-V CPU and AI processor IP to Japan's Leading-edge Semiconductor Technology Center (LSTC), which will use the technology to build its edge-focused AI accelerator. The most curious part of the announcement is that this accelerator will rely on a multi-chiplet design and the chiplets will be made by Japan's Rapidus on its 2nm fabrication process, and then will be packaged by the same company.

Under the terms of the agreement, Tenstorrent will license its datacenter-grade Ascalon general-purpose processor IP to LSTC and will help to implement the chiplet using Rapidus's 2nm fabrication process. Tenstorrent's Ascalon is a high-performance out-of-order RISC-V CPU design that features an eight-wide decoding. The Ascalon core packs six ALUs, two FPUs, and two 256-bit vector units and when combined with a 2nm-class process technology promises to offer quite formidable performance.

The Ascalon was developed by a team led by legendary CPU designer Jim Keller, the current chief executive of Tenstorrent, who used to work on successful projects by AMD, Apple, Intel, and Tesla.

In addition to general-purpose CPU IP licensing, Tenstorrent will co-design 'the chip that will redefine AI performance in Japan.' This apparently means that Tenstorrent  does not plan to license LSTC its proprietary  Tensix cores tailored for neural network inference and training, but will help to design a proprietary AI accelerator generally for inference workloads.

"The joint effort by Tenstorrent and LSTC to create a chiplet-based edge AI accelerator represents a groundbreaking venture into the first cross-organizational chiplet development in semiconductor industry," said Wei-Han Lien, Chief Architect of Tenstorrent's RISC-V products. "The edge AI accelerator will incorporate LSTC's AI chiplet along with Tenstorrent's RISC-V and peripheral chiplet technology. This pioneering strategy harnesses the collective capabilities of both organizations to use the adaptable and efficient nature of chiplet technology to meet the increasing needs of AI applications at the edge."

Rapidus aims to start production of chips on its 2nm fabrication process that is currently under development sometimes in 2027, at least a year behind TSMC and a couple of years behind Intel. Yet, if it starts high-volume 2nm manufacturing in 2027, it will be a major breakthrough from Japan, which is trying hard to return to the global semiconductor leaders.

Building an edge AI accelerator based on Tenstorrent's IP and Rapidus's 2nm-class production node is a big deal for LSTC, Tenstorrent, and Rapidus as it is a testament for technologies developed by these three companies.

"I am very pleased that this collaboration started as an actual project from the MOC conclusion with Tenstorrent last November," said Atsuyoshi Koike, president and CEO of Rapidus Corporation. "We will cooperate not only in the front-end process but also in the chiplet (back-end process), and work on as a leading example of our business model that realizes everything from design to back-end process in a shorter period of time ever."

Source: Tenstorrent

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  • ballsystemlord - Wednesday, February 28, 2024 - link

    Umm, what exactly was licensed on the RISC-V processor? RISC-V is open HW.
  • FWhitTrampoline - Wednesday, February 28, 2024 - link

    The RISC-V ISA and execution rules are open and free to utilize but the underlying Micro-Architecture that Tenstorrent created to implement the RISC-V ISA is Tenstorrent's IP. So the Instruction Decoders on the cores that break down the RISC-V ISA instructions into Micro-Ops(Single Micro-ops or Multiple Micro-ops) and the micro-op execution engine is all Tensetorrent's IP. The Cache subsystems and Memory controllers are all Tensetorrents's design etc.

    But there may be 3rd party SerDes IP from other providers as well as IP blocks that may be licensed from others if not created in-house. But really the SOC client may be the one licensing the 3rd party IP and Tensetorrent just providing a working Ascalon core/cores complex that can hardware interoperate with that client's hardware IP/3rd party licensed hardware IP.

    And all ISA are just execution templates with execution rules to follow and Memory Coherency models to enforce etc! But the actual hardware is not the ISA but a custom implementation engineered to execute the ISA.
  • Threska - Thursday, February 29, 2024 - link

    Right, some forget open hardware isn't the same as open software.
  • OreoCookie - Saturday, March 2, 2024 - link

    Even open software isn't the same. Linux is open source. Android isn't really open source: its development is not open, only releases are. Some functionality is contingent on device manufacturers entering licensing agreement with Google.

    The fact that RISC V is open is still an advantage. In the same way that Linux running on ARM-based server hardware benefits from the work Google and others have invested in the ARM port of Linux.
  • ballsystemlord - Thursday, February 29, 2024 - link

    The RISC-v creators used the open license... dang, even wikipedia just links to a news article that uses the catch-all phrase, "Open License". Fail.

    Ah, they used CC4. CC4 has a copy-left clause. I wonder why it doesn't appear to apply here, since the processor is obviously a derivative work, being an actual physical implementation of a textual description.
  • GeoffreyA - Friday, March 1, 2024 - link

    I understand what you're saying. It seems their stance is that the hardware implementation is separate from the specification. Only the specification is open and free to use. A RISC-V implementation, on the other hand, can be either closed or open source. According to their FAQ, the confusion is coming from the difference between open source and open standard, and RISC-V falls under the latter.

    "The closest analogy to the RISC-V specification is a book that defines words, like a dictionary. A dictionary can’t run programs.

    "If our company builds a RISC-V implementation, is it required to release its source code for the RISC-V core? // No, the source code can be completely closed."

  • ballsystemlord - Friday, March 1, 2024 - link

    Thanks, that makes things much clearer!
  • Yojimbo - Thursday, February 29, 2024 - link

    RISC-V is a swamp-in-waiting.
  • vladpetric - Monday, March 4, 2024 - link

    Microarchitecture - things like the front-end (branch prediction though not only), execution engine, back-end.

    Getting these right is a lot more complicated than the instruction set (decoding it, executing it, etc)
  • peevee - Tuesday, March 5, 2024 - link

    RISC-V by itself brings nothing compared to ARMv8. Prove me wrong.

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