Thermal Management on Stacked Silicon

With a standard processor design, there is a single piece of silicon doing all the work and generating the heat – it’s bonded to the package (which doesn’t do any work) and then depending on the implementation, there’s some adhesive to either a cooler or a headspreader then a cooler. When moving to a stacked chiplet design, it gets a bit more complicated.

Having two bits of silicon that ‘do work’, even if one is the heavy compute die and the other is an active interposer taking care of USB and audio and things, does mean that there’s a thermal gradient between the silicon, and depending on the bonding, potential for thermal hotspots and build-up. Lakefield makes it even more complex, by having an additional DRAM package placed on top but not directly bonded.

We can take each of these issues independently. For the case of die-on-die interaction, there is a lot of research going into this area. Discussions and development about fluidic channels between two hot silicon dies have been going on for a decade or longer in academia, and Intel has mentioned it a number of times, especially when relating to a potential solution of its new die-to-die stacking technology.

They key here is hot dies, with thermal hotspots. As with a standard silicon design, ideally it is best to keep two high-powered areas separate, as it gives a number of benefits with power delivery, cooling, and signal integrity. With a stacked die, it is best to not have hotspots directly on top of each other, for similar reasons. Despite Intel using its leading edge 10+ process node for the compute die, the base die is using 22FFL, which is Intel’s low power implementation of its 14nm process. Not only that, but the base die is only dealing with IO, such as USB and PCIe 3.0, which is essentially fixed bandwidth and energy costs. What we have here is a high-powered die on top of a low powered die, and as such thermal issues between the two silicon die, especially in a low TDP device like Lakefield (7W TDP), are not an issue.

What is an issue is how the compute die gets rid of the heat. On the bottom it can do convection by being bonded to more silicon, but the top is ultimately blocked by that DRAM die. As you can see in the image above, there’s a big air gap between the two.

As part of the Lakefield design, Intel had to add in a number of design changes in order to make the thermals work. A lot of work can be done with the silicon design itself, such as matching up hotspots in the right area, using suitable thickness of metals in various layers, and rearranging the floorplan to reduce localized power density. Ultimately both increasing the thermal mass and the potential dissipation becomes high priorities.

Lakefield CPUs have a sustained power limit of 7 watts – this is defined in the specifications. Intel also has another limit, known as the turbo power limit. At Intel’s Architecture Day, the company stated that the turbo power limit was 27 watts, however in the recent product briefing, we were told is set at 9.5 W. Historically Intel will let its OEM partners (Samsung, Lenovo, Microsoft) choose its own values for these based on how well the design implements its cooling – passive vs active and heatsink mass and things like this. Intel also has another factor of turbo time, essentially a measure of how long the turbo power can be sustained for.

When we initially asked Intel for this value, they refused to tell us, stating that it is proprietary information. After I asked again after a group call on the product, I got the same answer, despite the fact that I informed the Lakefield team that Intel has historically given this information out. Later on, I found out through my European peers that in a separate briefing, they gave the value of 28 seconds, to which Intel emailed me this several hours afterwards. This value can also be set by OEMs.

Then I subsequently found one of Intel’s ISSCC slides.

This slide shows that a basic implementation would only allow sustained power for 2.5 seconds. Adding in an adhesive between the top die and the DRAM moves up to 12.4 seconds, and then improving the system cooling goes up to 20 seconds. The rest of the improvements work below the compute die: a sizeable improvement comes from increasing the die-to-die metal density, and then an optimized power floor plan which in total gives sustained power support for 150+ seconds.

Lakefield: Top Die to Bottom Die Hybrid CPUs: Sunny Cove and Tremont


View All Comments

  • throAU - Monday, July 13, 2020 - link

    So, unless this can compete with the iPad Pro processor of the day, I just don't see the market. Windows 10 on ultra portable tablet type devices already sucks. So your realistic choices are android and iOS. Android has a suite of decently performing, already existent SOCs on the market, likely at far less cost than intel will no doubt try to charge for this. And no AVX-512? Only a single performance core? I just don't see it working out.

    I would have thought they'd be far better off not neutering the Sunny Cove core, and working with Microsoft/others on an API for workload queuing to the relevant core for a relevant code fragment. Treat the performance core as you would any other co-processor. Use thread affinity to bind specific UI threads to it. I'm sure there are methods that could be used but no - in order to run on unmodified platforms (that suck for the market segment they are aiming at anyway) - they crippled it.
  • serendip - Tuesday, July 14, 2020 - link

    Notebookcheck has a review comparing the Intel Lakefield and ARM models of the Galaxy Book S:m

    The results aren't pretty. For the same price of around $1000, the Lakefield version loses LTE in some markets, has equal or slightly less performance for CPU and GPU, but it has <10 hour battery life compared to the 8cx model's 16 hours. Despite all the fancy packaging, Lakefield is still half as efficient as Qualcomm's best, which makes it outclassed by Apple's silicon.

    The worst part about Lakefield on Windows is how it essentially performs as a quad core Atom chip most of the time. Ian's fears were realized.
  • throAU - Tuesday, July 14, 2020 - link

    This is pretty much exactly what I expected. Except the modern ARM processors have a better feature set than a crippled Lakefield chip. And there's less fragmentation in what they will/will not support vs. other ARM processors of the day.

    I expected Qualcomm to outclass it. It won't even be anywhere near close an A12Z and that's a processor from 12-18 months ago, which will no doubt be outclassed itself by whatever apple release late this year.
  • ballsystemlord - Wednesday, July 22, 2020 - link

    Spelling and grammar errors:

    "For those that are interested, Lakefield's PMICs are under the codenames Warren Cove and Castro Cover, and were developed in 2017-2018."
    I think you misspelled "cove":
    "For those that are interested, Lakefield's PMICs are under the codenames Warren Cove and Castro Cove, and were developed in 2017-2018."

    "Even those these CPUs are a 1+4 configuration,..."
    "though" not "those":
    "Even though these CPUs are a 1+4 configuration,..."

    "Another thing to note, which Intel glossed over, that most people are going to be really concerned about."
    Missing "is" and concerned about what?
    "Another thing to note, which Intel glossed over, is that most people are going to be really concerned about."

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