Thermal Management on Stacked Silicon

With a standard processor design, there is a single piece of silicon doing all the work and generating the heat – it’s bonded to the package (which doesn’t do any work) and then depending on the implementation, there’s some adhesive to either a cooler or a headspreader then a cooler. When moving to a stacked chiplet design, it gets a bit more complicated.

Having two bits of silicon that ‘do work’, even if one is the heavy compute die and the other is an active interposer taking care of USB and audio and things, does mean that there’s a thermal gradient between the silicon, and depending on the bonding, potential for thermal hotspots and build-up. Lakefield makes it even more complex, by having an additional DRAM package placed on top but not directly bonded.

We can take each of these issues independently. For the case of die-on-die interaction, there is a lot of research going into this area. Discussions and development about fluidic channels between two hot silicon dies have been going on for a decade or longer in academia, and Intel has mentioned it a number of times, especially when relating to a potential solution of its new die-to-die stacking technology.

They key here is hot dies, with thermal hotspots. As with a standard silicon design, ideally it is best to keep two high-powered areas separate, as it gives a number of benefits with power delivery, cooling, and signal integrity. With a stacked die, it is best to not have hotspots directly on top of each other, for similar reasons. Despite Intel using its leading edge 10+ process node for the compute die, the base die is using 22FFL, which is Intel’s low power implementation of its 14nm process. Not only that, but the base die is only dealing with IO, such as USB and PCIe 3.0, which is essentially fixed bandwidth and energy costs. What we have here is a high-powered die on top of a low powered die, and as such thermal issues between the two silicon die, especially in a low TDP device like Lakefield (7W TDP), are not an issue.

What is an issue is how the compute die gets rid of the heat. On the bottom it can do convection by being bonded to more silicon, but the top is ultimately blocked by that DRAM die. As you can see in the image above, there’s a big air gap between the two.

As part of the Lakefield design, Intel had to add in a number of design changes in order to make the thermals work. A lot of work can be done with the silicon design itself, such as matching up hotspots in the right area, using suitable thickness of metals in various layers, and rearranging the floorplan to reduce localized power density. Ultimately both increasing the thermal mass and the potential dissipation becomes high priorities.

Lakefield CPUs have a sustained power limit of 7 watts – this is defined in the specifications. Intel also has another limit, known as the turbo power limit. At Intel’s Architecture Day, the company stated that the turbo power limit was 27 watts, however in the recent product briefing, we were told is set at 9.5 W. Historically Intel will let its OEM partners (Samsung, Lenovo, Microsoft) choose its own values for these based on how well the design implements its cooling – passive vs active and heatsink mass and things like this. Intel also has another factor of turbo time, essentially a measure of how long the turbo power can be sustained for.

When we initially asked Intel for this value, they refused to tell us, stating that it is proprietary information. After I asked again after a group call on the product, I got the same answer, despite the fact that I informed the Lakefield team that Intel has historically given this information out. Later on, I found out through my European peers that in a separate briefing, they gave the value of 28 seconds, to which Intel emailed me this several hours afterwards. This value can also be set by OEMs.

Then I subsequently found one of Intel’s ISSCC slides.

This slide shows that a basic implementation would only allow sustained power for 2.5 seconds. Adding in an adhesive between the top die and the DRAM moves up to 12.4 seconds, and then improving the system cooling goes up to 20 seconds. The rest of the improvements work below the compute die: a sizeable improvement comes from increasing the die-to-die metal density, and then an optimized power floor plan which in total gives sustained power support for 150+ seconds.

Lakefield: Top Die to Bottom Die Hybrid CPUs: Sunny Cove and Tremont
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  • Valantar - Sunday, July 5, 2020 - link

    Uhm, I have to ask, did you write this comment eight months ago? AMD has been kicking Intel's butt in 15W laptops since the first Renoir laptops hit the streets. While that did take a while after the initial presentation, their advantage is nonetheless significant both in performance and power draw. Reply
  • serendip - Monday, July 6, 2020 - link

    AMD doesn't have anything in the 5W TDP range. Not yet, anyway. The problem is that Lakefield brings middling performance at a high price. Intel already has 5W and 4W parts, check out the Pentium 4425Y and m3-8100Y in the Surface Go 2. Those chips are much cheaper and easier to fab than Lakefield and they bring equal or higher performance. Reply
  • Kangal - Tuesday, July 7, 2020 - link

    The best sku chipset that AMD makes in the "15W bracket" is the 4800U. However, that's with the TDP-down as it's not a proper 15W part. Plus, there are no laptops with that combination yet. The Lenovo Yoga Slim7 has the chipset, but it is at the 25W bracket, and apparently that goes much higher during use when possible.

    So no, AMD isn't quite kicking Intel's butt in the Ultrabook segment yet. Maybe in 6 months, when yields improve and more vendors join. But for now, Intel is still the dominant force in the Thin & Light segment. AMD they're killing it at the Regular Laptop market, the Entire Desktop Market, the Server market, and the Console market. However, ARM is pretty much going to take over the Server Market now that the big companies are moving that way, and since Linux drivers have matured on ARMv8_64. The laptop segment is safe for now, but the new Macs might cause other vendors to think beyond Windows, or think beyond x86. The Console segment and Desktop segments are safe for now (and for at least this decade).
    Reply
  • Spunjji - Friday, July 10, 2020 - link

    That's an arbitrary distinction if ever I saw one. By that definition, Ice Lake is a 28W part operating in "TDP down" to 15W.

    AMD could conceivably laser 4 cores and 60% of the GPU off a Renoir chip, drop the clocks and end up with a "5W" part not dissimilar to Intel's M3 series. It wouldn't make any sense for them to do so, though, because they can't make enough chips as it is and it wouldn't really buy them any meaningful market share.
    Reply
  • Kangal - Friday, July 10, 2020 - link

    I didn't discount the 4800U at all. I merely stated the fact that it is, in fact, a 25W chipset and it can operate at 15W with TDP-down. I'm not sure you quite understand this tier system.

    But anyways, my point was that AMD's best 15W option is the 4800U, but we don't know how it actually performs because there are no devices out there. From what we can speculate, it should be very competitive, but Intel really has championed the Ultrabook market in the last decade. So for all intents and purposes, Intel is probably still ahead here by a hair, yet they could've had a larger lead if they implemented the above design I tried to explain. Too bad. AMD will humiliate/supersede them completely in a year or two at this pace.
    Reply
  • Spunjji - Monday, July 6, 2020 - link

    "And AMD would struggle to fit those technologies into a 8-core laptop processor, so there would be no threat from above."

    Boy, you really need to keep up with the news...
    Reply
  • Kangal - Tuesday, July 7, 2020 - link

    No, you didn't read that correctly.
    AMD doesn't have any 8-core processor on their 16nm/14nm/12nm node, that is, confined to the thermal profile of a laptop. I was saying Intel needed to release the processor that I outlined, and release it years ago. And if they did that, then their only competition would be Renoir/Ryzen-4000, and even then AMD would lose on the low-voltage (Ultrabook) market and win on the regular (Laptop) market.

    See the above comment by serendip. AMD is working on having lower and lower voltage chips. Their lowest power one I think is still the V1605B embedded chip. But right now, that small company is really stretched thin. They're working on Servers, on HDD optimisations, on making GPUs, on optimising GPUs, on making console processors, on desktops, laptops, and a few other budget options.

    By the time AMD actually properly polishes the driverset for laptops/battery drain, it's going to be another year. But hopefully, on the next set of chips they update the graphics (from Vega to RDNA). It's possible they might ditch the monolithic design of their mobile chips, and shift those over to a chiplet design as well. This will take a hit to performance, and to efficiency... but on the bright side it should mean even cheaper processors to vendors and consumers-alike.
    Reply
  • Spunjji - Friday, July 10, 2020 - link

    I think I understand now, but the phrasing was confusing! Reply
  • eastcoast_pete - Thursday, July 2, 2020 - link

    It's beyond embarrassing, it's borderline idiotic. Intel's "performance" cores have one unique differentiator going for them, and that is the ability to execute AVX, especially AVX2 and AVX512 instructions. Doing what they did means they basically gelded their own big core, and this gelding won't win any performance crowns.
    I sort of get why it's hard to have a scheduler trying to work with cores that have different capabilities, but is it really impossible to have one that makes it a hard and fast rule that if an AVX instruction is called for, the big core gets fired up? Now, I am not able to program one of these myself, but, as a user, I would rather pay a little power consumption penalty and have a real Sunny Cove-like large core than an overgrown Atom as the "performance" core. Big mistake.
    Reply
  • brantron - Thursday, July 2, 2020 - link

    The trouble with AVX on the Sunny Cove core is it will still only be one core.

    So add another, and call it...Ice Lake Y? Wait a minute... :p

    After more than a decade, Atom for PC still looks like a square peg in a round hole.
    Reply

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