As part of the second leg of TSMC's spring technology symposium series, the company offered an update on the state of its 3nm-class processes, both current and future. Building on the back of their current-generation N3E process, the optical shrink of this process technology, N3P, is now on track to enter mass production in the second half of 2024. Thanks to that shrink, N3P is expected to offer both increased performance efficiency as well as increased transistor density over N3E.

N3E in Production, Yielding Well

With N3E already in volume production, TSMC is reporting that they're seeing "great" yields on the second-generation 3nm-class process note. According to the company, the D0 defect density of N3E is at relative parity with N5, matching the defect rate of the older node for the same point in its respective lifecycle. This is no small feat, given the additional complexities that come with developing one last, ever-finer generation of FinFET technology. So for TSMC's bleeding-edge customers such as Apple, who just launched their M4 SoC, this is allowing them to reap the benefits of the improved process node relatively quickly.

"N3E started volume production in the fourth quarter of last year, as planned," a TSMC executive said at the event. "We have seen great yield performance on customers' products, so they did go to market as planned."

TSMC's N3E node is a relaxed version of N3B, eliminating some EUV layers and completely avoiding the usage of EUV double patterning. This makes it a bit cheaper to produce, and in some cases it widens the process window and yields, though it comes at the cost of some transistor density.

N3P on Track For Second-Half 2024

Meanwhile, looking towards the immediate future at TSMC, N3P has finished qualification and its yield performance is close to N3E, according to the company. Being an optical shrink, the N3P node is set to enable processor developers to either increase performance by 4% at the same leakage or reduce power consumption by 9% at the same clocks (previously the range was between 4% ~ 10% depending on design). The new node is also set to boost transistor density by 4% for a 'mixed' chip design, which TSMC defines as a processor consisting of 50% logic, 30% SRAM, and 20% analog circuits.

Advertised PPA Improvements of New Process Technologies
Data announced during conference calls, events, press briefings and press releases
Power -25-30% -32% -5% ~ 10% higher
Performance +10-15% +18% +5% +5%
Fmax @ 1.2V
Chip Density ? ? 1.04x same
SRAM Cell Size 0.0199µm² (-5% vs N5) 0.021µm² (same as N5) ? ?
Late 2022 H2 2023 H2 2024 2025

While it looks like the original N3 (aka N3B) will have a relatively muted lifecycle since Apple has been its only major customer, N3E will be adopted by a wide range of TSMC's customers, which includes many of the industry's biggest chip designers. 

Since N3P is an optical shrink of N3E, it is compatible with its predecessor in terms of IP blocks, process rules, electronic design automation (EDA) tools, and design methodology. As a result, TSMC expects the majority of new tape outs to use N3P, not N3E or N3. This is logical as N3P provides higher performance efficiency than N3E at a lower cost than N3.

The most important aspect of N3P is that it is on track to be production ready in the second half of this year, so expect chip designers to adopt it straight away. 

"We have also successfully delivered N3P technology," the TSMC executive said. "It has passed qualification and yield performance is close to N3E. [The process technology] has also received product customer tape outs and will start on production in the second half of this year. Because of [PPA advantages] of N3P, we expect the majority of tape outs on N3 to go to N3P."

Source: European Technology Symposium 2024



View All Comments

  • ballsystemlord - Wednesday, May 15, 2024 - link

    I'm kinda surprised that the chip density numbers for N3 and N3E are still not known despite being in mass production for some time now. Reply
  • evanh - Wednesday, May 15, 2024 - link

    What little info is there suggests it's not really different from the N5's. Which is a tad embarrassing given the rather relatively large step in node numbering.

    I guess they're already up against the wall without high-NA equipment. That doesn't bode well.
  • evanh - Wednesday, May 15, 2024 - link

    Speaking of, 100% of all High-NA shipments are destined for USA this year. Line #2 already went to an unnamed recipient, speculated to be an IBM affiliated research facility. Speculating ... Maybe next year's batch goes to US based new fabs for TSMC, Samsung and co ... EU might get a look in since they're building the stuff ... nothing for Japan, Taiwan or Korea. Reply
  • my_wing - Wednesday, May 15, 2024 - link

    No TSMC will not install its first EUV High NA machine in the US, it has to be in Taiwan, they build a billion dollar research lab there, just like what Intel is doing.

    EU is not might get a look, EU is going to get one in 2027, that is Intel Germany, it takes 3 months to set the machine up (although is the new one i.e. take longer but the machine arrived in the US in Dec 2023 and only in weeks time that first lights-on), the schedule is that Q4 2027 Germany online i.e. the machine needed to be there Q1 2027, assuming there isn't just 1 EUV machine.

    The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know.

    N5/N3ABCXYZ they all just marketing name, basically is optimized FinFET, N2ABCXYZ is just the segment that will be GAA, A123789 will be BSPD. It did not link to anything from other manufacturer, so the financial fools out there comparing Intel 18A to TSMC A16, the number is meaningless, once the true number coming from the transistor.

    Some other TSMC PR researcher also mentioned that TSMC N3P better than Intel 18A, but from the leak clock of Arrow Lake (20A) and with a true increase of silicone area utilization of 6%, these fact/ PR Research Paper make me believes that Intel 20A better than N3P, because these TSMC IR/PR information is not scientific at all, I am treating this as an IR tricks to pop up share price.

    If you are saying single patterning yes, it hit the wall, but multi-pattering No. In answering the density issues, on the transistor layer they anyway needed multiple steps / patterning as it needed to build the structure of the transistor i.e. GAA.

    The Wall issues is that TSMC felt like they can get away with it with AI (CuLitho), I am not sure, but it is not just High NA we are talking about Applied Materials Sculpta will also help to extend "the wall" mentioned. But TSMC is doing neither of those i.e. No High NA No Sculpta.
  • ballsystemlord - Wednesday, May 15, 2024 - link

    "The TSMC density count is based on a ratio of transistor, so Apple M3 or so did not come with the ration that TSMC specify therefore they said they don't know."

    I was of the understanding that TSMC used test wafers to determine node density. Others have speculated that it's an ARM design which the calculation is based off of. In any case, we all know that these node numbers are just numbers. It's what the density improvement is that makes a new node new, as opposed to a "+" node like Intel kept doing with 14nm.
  • dwbogardus - Thursday, May 16, 2024 - link

    Every process node has three orthogonal performance vectors: density, power, and frequency. Various nodes are intentionally developed to optimize one of these, usually at the expense of the others. While Intel took years to get it's "10 nm" node to acceptable yield levels, they still had to ship successive generations of products with at least incremental frequency improvements on the 14 nm process which did yield well. No surprise that they continued to refine the 14 nm process with +, ++, and +++, and took much grief for it. But they did wind up with the world's most speed performant 14 nm process node, although it was too late to be relevant or appreciated. Reply
  • evanh - Thursday, May 16, 2024 - link

    So, TSMC has assigned new numbers relative to its own numbering, 5 down to 3. That's a 40% smaller dimension. Where in that selection of four already is there an actual density to match? N3-plain looks to be the best at just 5% reduction. Reply
  • nandnandnand - Thursday, May 16, 2024 - link

    +43% transistor density according to slides and estimates, maybe lower. At least one slide looks obsolete because we know SRAM is not gaining +20%.

    SRAM's lack of improvement should be ignored because it has apparently hit a scaling wall and won't shrink much more. Maybe that changes with GAAFETs (N2). If it doesn't, 3D stacking of SRAM is the obvious way forward.

    Even if density improvements are slowing, these new nodes can still be valuable, mostly for the power savings. A 35% reduction in power consumption can be very helpful.
  • Terry_Craig - Thursday, May 16, 2024 - link

    Yeah, It's a bit unrealistic, CPU and GPUs currently have large amounts of cache:

    In certain cases, cache occupies more than 50% of the die.
  • OreoCookie - Saturday, May 18, 2024 - link

    Another aspect ist that price is often not included in “better”. Intel's 10 nm node was far from profitable, and this wasn't just a function of yield. If you need more steps to produce said product, you decrease overall throughput. At what point are Intel's nodes profitable? And at what point does Intel get the margins it would like.

    Intel is taking more risks than TSMC at the moment, because they have to. Technology-wise, this is pretty cool, their push for BSPDN is particularly important not just for what it is, but what technologies that manufacturing capability will enable in the future. Intel will have to be significantly better and/or cheaper than TSMC to attract volume customers.

Log in

Don't have an account? Sign up now