Tenstorrent this week announced that it had signed a deal to license out its RISC-V CPU and AI processor IP to Japan's Leading-edge Semiconductor Technology Center (LSTC), which will use the technology to build its edge-focused AI accelerator. The most curious part of the announcement is that this accelerator will rely on a multi-chiplet design and the chiplets will be made by Japan's Rapidus on its 2nm fabrication process, and then will be packaged by the same company.

Under the terms of the agreement, Tenstorrent will license its datacenter-grade Ascalon general-purpose processor IP to LSTC and will help to implement the chiplet using Rapidus's 2nm fabrication process. Tenstorrent's Ascalon is a high-performance out-of-order RISC-V CPU design that features an eight-wide decoding. The Ascalon core packs six ALUs, two FPUs, and two 256-bit vector units and when combined with a 2nm-class process technology promises to offer quite formidable performance.

The Ascalon was developed by a team led by legendary CPU designer Jim Keller, the current chief executive of Tenstorrent, who used to work on successful projects by AMD, Apple, Intel, and Tesla.

In addition to general-purpose CPU IP licensing, Tenstorrent will co-design 'the chip that will redefine AI performance in Japan.' This apparently means that Tenstorrent  does not plan to license LSTC its proprietary  Tensix cores tailored for neural network inference and training, but will help to design a proprietary AI accelerator generally for inference workloads.

"The joint effort by Tenstorrent and LSTC to create a chiplet-based edge AI accelerator represents a groundbreaking venture into the first cross-organizational chiplet development in semiconductor industry," said Wei-Han Lien, Chief Architect of Tenstorrent's RISC-V products. "The edge AI accelerator will incorporate LSTC's AI chiplet along with Tenstorrent's RISC-V and peripheral chiplet technology. This pioneering strategy harnesses the collective capabilities of both organizations to use the adaptable and efficient nature of chiplet technology to meet the increasing needs of AI applications at the edge."

Rapidus aims to start production of chips on its 2nm fabrication process that is currently under development sometimes in 2027, at least a year behind TSMC and a couple of years behind Intel. Yet, if it starts high-volume 2nm manufacturing in 2027, it will be a major breakthrough from Japan, which is trying hard to return to the global semiconductor leaders.

Building an edge AI accelerator based on Tenstorrent's IP and Rapidus's 2nm-class production node is a big deal for LSTC, Tenstorrent, and Rapidus as it is a testament for technologies developed by these three companies.

"I am very pleased that this collaboration started as an actual project from the MOC conclusion with Tenstorrent last November," said Atsuyoshi Koike, president and CEO of Rapidus Corporation. "We will cooperate not only in the front-end process but also in the chiplet (back-end process), and work on as a leading example of our business model that realizes everything from design to back-end process in a shorter period of time ever."

Source: Tenstorrent



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  • GeoffreyA - Wednesday, March 6, 2024 - link

    Technically, there's likely not much of a difference in the result, though I believe it's simpler. Being free and open is good. Reply
  • do_not_arrest - Wednesday, March 6, 2024 - link

    RISC-V offers 128-bit addressing. Who knows if anybody is using it yet - probably not. RISC-V is also free. Arm has hefty license fees and also per-chip royalties. Reply
  • GeoffreyA - Thursday, February 29, 2024 - link

    Ascalon sounds quite strong. It will be interesting to see how it performs. Reply
  • Dante Verizon - Thursday, February 29, 2024 - link

    If it were next year I'd be impressed, but by 2027 the competition will be up to scratch... Reply
  • Findecanor - Thursday, February 29, 2024 - link

    I'm afraid that for Tenstorrent it is AI first, and RISC-V second, and we're never going to see a general purpose CPU from them — only as control processor in some kind of AI accelerator. Reply
  • OreoCookie - Saturday, March 2, 2024 - link

    Why is that necessarily a bad thing?

    RISC V is very successful in many places where e. g. interoperability is not as important. Harddrive controllers is an example that comes to mind (to my knowledge, Western Digital uses RISC V cores in its HD controllers). But it need not take over all niches.

    Part of the licensing agreement with ARM are tests that your cores comply with the ARM ISA spec. For RISC V such an ultimate authority is missing. This has advantages and disadvantages. It is great if you don't actually need interoperability. But it is detrimental if several companies build their own cores and subtle differences lead to problems.
  • Blastdoor - Friday, March 1, 2024 - link

    Funny to see how Chinese malevolence towards Taiwan has revitalized American and Japanese semiconductor manufacturing. Was that the goal, comrade Xi? Or was the goal to revitalize American and Japanese military industrial complex? Because you’re doing that too. Also, the EU now doesn’t trust you, nor do your neighbors. All to threaten a little island that you can only control if you destroy, leaving it useless to you.

    I’d love to play a game of multiplayer Civ with this dope.
  • GeoffreyA - Friday, March 1, 2024 - link

    Well, the beautifully-moral, US-backed Israel is playing a brilliant game of Civilization in the sands of Palestine as we speak. At this rate, they'll be teaching even China a thing or two. Reply
  • do_not_arrest - Wednesday, March 6, 2024 - link

    China has nukes. China can reduce costs and undercut prices by stealing western technology and IP. Xi cares what we think about as much as Putin. The whole world needs to finally agree to build an economic wall around these countries until they wake up and join the 21st century. ISR too. SA too. Heck the whole ME. Reply
  • peevee - Tuesday, March 5, 2024 - link

    "2nm" is what really, 20nm transistor pitch? 30nm? 40nm? So tired of the fraud. Reply

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