Samsung Foundry has been killing it of late. Remember when Intel used to be years ahead of the rest? In the short span of half a decade, Samsung has eliminated the gap completely, and clearly overtaken TSMC.
What is exciting is Globalfoundries and AMD has access to Samsung's tech. After decades, AMD might finally be ahead of Intel on process!
7nm is exciting though. Samsung's EUV versus Intel's silicon-replacement. I have a feeling someone is going to have a significant advantage.
I am no expert (perhaps someone else can chime in), but my understanding is that when a company produces a '7nm' chip, then that 7nm can measure almost anything. It can be the size of the electronic structures, or the resolution at which it can 'print', or the spacing between structures, etc. etc. etc. Plus, not everything is going to be at 7nm, only certain parts will be. Often times it is only simple repeating structures that get the ultra small 7nm treatment, while other parts of the chip continue to have larger simpler processes applied to them so the failure count stays acceptable. Plus, different processes at the same nm level have different results. Some bleed more electrons, some have more cross-talk and interferance within the chip, etc. etc. etc.
Long story short, not all 'nm' ratings are made equal, and while some companies are getting good at getting certain parts of a die shrunk down, Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues.
I'm not sure that's right. The nm length almost universally means the width of the channel in the transistors (sometimes called the smallest feature size). Also I'm not certain mixing nodes in a foundry happens very often but I simply don't know. It wouldn't make a lot of the previous transistor count estimations from die size and process make a lot of sense and those are usually accurate. Also if Samsung really is making transistors smaller than Intel then they do have a technological advantage. Things are not looking great for Intel atm. They won't die overnight but their mismanagement over the past decade will hurt them.
The size rating is indeed the smallest feature size that can be printed and is usually applied to the channel width. However Transistors are more than a single dimension in size, these days they are even 3 dimensional.
Intel's process nodes while being nominally the same feature size in name, are much more dense and usually of a higher quality. For example both TSMC and Samsung/GF use 20nm level sizing for their metal layers at their 16/14nm nodes, whereas intel actually has 14nm sizing.
It should be noted that when talking about the sizing at this point they are just marketing names.
"Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues."
These are totally unfounded claims. There is no useful sense in which Intel has "smallest die size", we have no idea what Intel yields are compared to Samsung or TSMC, we have no idea what field failure rates are (but they are spectacularly low for all three companies), and there are no process-specific "other issues" that apply to some foundries and not others.
TSMC appears to have better ultra-tight packaging (InFO), and certainly it (and Samsung's) packaging is a lot more useful to its target customers insofar as it enables putting together packages from a variety of different chips. Intel does have a history of tight packages for the items it ships (starting from putting a separate L2 on the same package all those years ago), now with things like CrystalWell, but doesn't seem to be as flexible as TSMC, presumably because it hasn't needed to be.
Well, "14nm" is only PR name. It has very little to do with real dimensions of anything. It used to be size of the smallest feature process can produce. Even if it were still true (doubt it), size of components differs. This is good example: http://pc.watch.impress.co.jp/img/pcw/docs/670/675...
It's nowhere close. Samsung's 10nm will be roughly equivalent to Intel's 14nm in density. Where Samsung currently holds an advantage is using fewer layers.
Intel's SRAM size is a full 20% smaller than TSMC/Samsung. This allows cache to be super small, and cache normally takes up a 1/3 of the chip. 20% is huge when cache is so prevalent in chips these days.
Intel's Gate Pitch, M1 Pitch and Fin Pitch is also smaller.
The technology 'node' name used to represent the actual channel length of the transistor at 250nm and 130 nm nodes. However, that stopped being true quite a while ago (around 65nm, when the actual channel length was close to 35-40nm). Fabs kept making material changes (strain, high-K dielectrics, metal-gates, etc.) to improve performance every node while the channel length remained constant, close to 30nm for technology nodes from 45nm, down to 22nm. These are all 'Intel nodes' btw. Foundries have followed a slightly different naming convention, where they go with half-nodes such as 28nm, 20nm and 14nm. Anyway, what really matters is probably gate-pitch and metal-pitch and not the channel length or the technology node name, really.
Traditionally, foundries have offered tighter metal-pitches, because they were catering to high-density low-cost SoC customers, while Intel had more aggressive transistors and poly pitches, but relaxed metal pitches because they were going for higher performance laptop/desktop/server markets. Post 20nm, Intel and foundries have completely different definitions of the technology nodes....and the 'X nm' name does not mean anything real. For example, Intel's 14nm technology node has no feature that is exactly 14nm in dimension. And the same is true for Samsung's 14nm node. They have a certain gate-pitch and metal-pitch, which give us some indication of the actual density that you can get in the technology node. however, as lithography becomes more and more difficult, printing these features become tougher and the actual density suffers. Hence, it is completely possible that you can get denser and higher-performing chips using a more relaxed gate/metal pitch combination and not scaling as fast as your competition. All these things are considered when determining the next technology node by these fabs and hence the raw dimension numbers might not match our expectations. Also, it is completely incorrect to compare two technology nodes from different companies just based on a few dimensional parameters.
In short, it is completely true that Samsung's 14nm/10nm/7nm definition is unequal/different to Intel's. And so is TSMC's too...so all three foundries end up with different definitions and the only way to compare them is to look at power/performance/area/cost trends of taped-out chips.
lol not anymore. The HD 520 is faster than pretty much all AMD offerings in their normal APUs and the Iris Graphics blow the rest to pot. In addition, quite a few games are CPU-limited and Intel is just so much faster.
I don't think Samsung has clearly overtaken TSMC. From what I've read, Apple has chosen TSMC for its A9X and A10 SOCs because they are happier with TSMCs offerings than Samsung's.
In addition, you can find analyses of the various processes about how Intel's 14nm has distinct advantages over TSMC's 16nm and Samsung's 14nm. AMD is not going to be ahead of Intel in process
Apple's preference for TSMC is heavily influenced by other factors. Samsung is a rather large influential competitor to Apple in the smartphone and tablet market. TSMC is not. As long as TSMC-produced chips are up to snuff they'll give preference to them. In the future TSMC may fall behind again (like when Samsung transitions to 10nm) and they may be forced to look elsewhere again (Samsung, GloFo) but right now they're doing well.
"Samsung has eliminated the gap completely, and clearly overtaken TSMC" Based on what? They have comparable performance today (The Apple A9 is the most obvious example of this), and their 10nm and 7nm roadmaps seem similar. TSMC has not stated definitely that they will use EUV for 7nm, but has given dates (risk production in 2017, volume production in 2018), Samsung has said they will use EUV but has not given dates.
As for claiming that TSMC/Samsung's processes do not match their Intel equivalents, again in the A9 /A9Xwe have a test case. At comparable power budgets, Apple's chip gives comparable CPU performance and higher GPU performance in comparable silicon area. That's all that's required to say that the processes are comparable. Sure Intel wins in some areas (smaller transistors and metal features) but it loses in others (restricted layout rules compared to Samsung/TSMC). Practically this all appears to even out when all three processes are used by experts.
[Realistically, I think, you have to score Samsung and TSMC as coming out ahead by this metric. Intel's CPUs have been optimized over thirty year, and each new CPU has everything about it tightly matched to the precise Intel process. Apple has been in the business for a much shorter length of time, and is targeting two distinct processes --- so there is a limit to how much process-specific optimization they can engage in, and probably a lot more automatic rather than manual layout --- and yet they achieve similar performance...]
"Based on what? They have comparable performance today (The Apple A9 is the most obvious example of this)"
Yet TSMC chips are larger than those made by Samsung (by about 10%).
So to answer your question, based on process efficiency (density). Samsung can simply cram ~10% more transistors into same area, potentially leading to ~10% performance improvement (the benefit of which is easiest to manifest with highly-parallelized designs such as GPUs).
This 7nm tech probably applies to small mobile chips only. If would be great but i don't think AMD will get access to any 7nm tech for their big desktop/server chips ahead of Intel anytime soon.
As an electronics engineer that actually works in the industry, it's always funny reading the comments of the utterly clueless. Keep it up, anandtech commenters!
Regarding the defect density... if it was 0.2 per mm^2, then using http://www.isine.com/DieYieldCalculator.html we get for the ~10x10mm Apple A9 a yield of over 82%, which is pretty good for a fully working die.
Also why can't Samsung buy AMD already? Imagine what powerful competition that could create for Intel? At least if Samsung was committed to designing chips. Right now I'm not convinced they are.
PC cpu is not atractive area to compete. Mobile cpu has better revenues and it is crovong market and PC is declining. Why invest in something that is not interesting. So there is not any reason for Samsung to buy AMD. Well the gpu part may be interesting, but AMD is not selling the only apartment that is making Profit for them.
Samsung would have no interest in x86 tech, Apple on the other hand will keep selling Macs for years to go so they definitely wouldn't want to be at the hands of Intel.
>IBM >litographic tech >Samsung >ahead of Intel >guaranteed at that
IBM is nothing but a overmanaged slaughterhouse for its employees, trying to turn into outright patent troll. And Samsung always promises and never delivers. I guess they make a good match.
Hmm...my guess would be based on the fact that E-beam lithography takes twice as long (at minimum) to make a mask at 7 nm compared to 10 nm. So either double the time or double the cost compared to 10 nm and something has to give.
"The Olympus-SoC place and route platform is also certified for use at 10nm, with a comprehensive colored design methodology covering floorplanning, placement, extraction, routing and chip finishing requirements. To address the particular challenges of FinFET manufacturing, the platform supports M1 triple patterning, color shifting, non-uniform tracks, mask- and width-dependent spacing rules, and other new capabilities. Active deployment is underway at multiple mutual customers."
Triple patterning already qualified for Samsung 10nm M1.
Where are they saying they'll use EUV? If anything they are saying that they won't. We are reviewing...... means yeah sure maybe at some point if it is ready and that's pretty much a no.
We had a call with Samsung on Thursday. They were rather explicit about intending to use EUV at 7nm (though obviously they still have challenges to resolve).
With news like this, I think Intel must be panicking. They used to have a good lead over the rest of the fabs, and thus, also gives their chips an edge in terms of performance vs power efficiency. With others catching up with them, that edge is gone and also making their effort to increase market shares vs ARM chips harder.
In 2008, Intel published (link below) that EUV had a fundamental shot noise problem, so that dose would have to keep increasing with smaller size. So source power has to keepincreasing. That's the real reason EUV could never be implemented.
I just can't help myself :) Still there is funny peoples with their "AMD will, shall, could, ..." AMD have nothing significant! They simply can wait someone to give them something :) --- And now on the matter: to have X nm process is one thing, to have ability to produce effectively large dies ... is completely different! --- Live long & prosper !
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clinton_goh - Friday, April 22, 2016 - link
Thanks for the update. I was wondering if you could update the source for this? Link seems broken. Thanks.clinton_goh - Friday, April 22, 2016 - link
It's working now.trane - Friday, April 22, 2016 - link
Samsung Foundry has been killing it of late. Remember when Intel used to be years ahead of the rest? In the short span of half a decade, Samsung has eliminated the gap completely, and clearly overtaken TSMC.What is exciting is Globalfoundries and AMD has access to Samsung's tech. After decades, AMD might finally be ahead of Intel on process!
7nm is exciting though. Samsung's EUV versus Intel's silicon-replacement. I have a feeling someone is going to have a significant advantage.
T1beriu - Friday, April 22, 2016 - link
You would be correct if Samsung's 14nm/10nm/7nm were equal to Intel's.halcyon - Friday, April 22, 2016 - link
How is Samsung's 14nm/10nm/7nm unequal to Intel's? Can you explain? I don't know.CaedenV - Friday, April 22, 2016 - link
I am no expert (perhaps someone else can chime in), but my understanding is that when a company produces a '7nm' chip, then that 7nm can measure almost anything. It can be the size of the electronic structures, or the resolution at which it can 'print', or the spacing between structures, etc. etc. etc. Plus, not everything is going to be at 7nm, only certain parts will be. Often times it is only simple repeating structures that get the ultra small 7nm treatment, while other parts of the chip continue to have larger simpler processes applied to them so the failure count stays acceptable.Plus, different processes at the same nm level have different results. Some bleed more electrons, some have more cross-talk and interferance within the chip, etc. etc. etc.
Long story short, not all 'nm' ratings are made equal, and while some companies are getting good at getting certain parts of a die shrunk down, Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues.
willis936 - Friday, April 22, 2016 - link
I'm not sure that's right. The nm length almost universally means the width of the channel in the transistors (sometimes called the smallest feature size). Also I'm not certain mixing nodes in a foundry happens very often but I simply don't know. It wouldn't make a lot of the previous transistor count estimations from die size and process make a lot of sense and those are usually accurate. Also if Samsung really is making transistors smaller than Intel then they do have a technological advantage. Things are not looking great for Intel atm. They won't die overnight but their mismanagement over the past decade will hurt them.menting - Friday, April 22, 2016 - link
that was true a few years back, but it's not true anymore.tuxfool - Friday, April 22, 2016 - link
The size rating is indeed the smallest feature size that can be printed and is usually applied to the channel width. However Transistors are more than a single dimension in size, these days they are even 3 dimensional.Intel's process nodes while being nominally the same feature size in name, are much more dense and usually of a higher quality. For example both TSMC and Samsung/GF use 20nm level sizing for their metal layers at their 16/14nm nodes, whereas intel actually has 14nm sizing.
It should be noted that when talking about the sizing at this point they are just marketing names.
name99 - Friday, April 22, 2016 - link
"Intel still holds the crown for having the smallest die size applied to the majority of their chips, while retaining a good failure rate, and with minimal other issues."These are totally unfounded claims. There is no useful sense in which Intel has "smallest die size", we have no idea what Intel yields are compared to Samsung or TSMC, we have no idea what field failure rates are (but they are spectacularly low for all three companies), and there are no process-specific "other issues" that apply to some foundries and not others.
TSMC appears to have better ultra-tight packaging (InFO), and certainly it (and Samsung's) packaging is a lot more useful to its target customers insofar as it enables putting together packages from a variety of different chips. Intel does have a history of tight packages for the items it ships (starting from putting a separate L2 on the same package all those years ago), now with things like CrystalWell, but doesn't seem to be as flexible as TSMC, presumably because it hasn't needed to be.
patrickjp93 - Friday, April 22, 2016 - link
Intel's 22nm yield rate for die sizes of 450 mm sq. is 89%. Samsung doesn't even produce chips that big, and TSMC's is a measly 71%medi03 - Sunday, April 24, 2016 - link
I thought things are expensive because of huge R&D and infrastructure investments.Are material costs actualy that important in this context?
qap - Friday, April 22, 2016 - link
Well, "14nm" is only PR name. It has very little to do with real dimensions of anything. It used to be size of the smallest feature process can produce. Even if it were still true (doubt it), size of components differs. This is good example:http://pc.watch.impress.co.jp/img/pcw/docs/670/675...
extide - Friday, April 22, 2016 - link
They are close, but definitely behind Intel. See this link for a easy visual description:http://images.teraknor.net/Cell-SizeComparison.png
patrickjp93 - Friday, April 22, 2016 - link
Are you joking? http://www.eetimes.com/document.asp?doc_id=1328866It's nowhere close. Samsung's 10nm will be roughly equivalent to Intel's 14nm in density. Where Samsung currently holds an advantage is using fewer layers.
jasonelmore - Friday, April 22, 2016 - link
Intel's SRAM size is a full 20% smaller than TSMC/Samsung. This allows cache to be super small, and cache normally takes up a 1/3 of the chip. 20% is huge when cache is so prevalent in chips these days.Intel's Gate Pitch, M1 Pitch and Fin Pitch is also smaller.
https://www.semiwiki.com/forum/content/3759-intel-...
saurabhr8here - Monday, April 25, 2016 - link
The technology 'node' name used to represent the actual channel length of the transistor at 250nm and 130 nm nodes. However, that stopped being true quite a while ago (around 65nm, when the actual channel length was close to 35-40nm). Fabs kept making material changes (strain, high-K dielectrics, metal-gates, etc.) to improve performance every node while the channel length remained constant, close to 30nm for technology nodes from 45nm, down to 22nm. These are all 'Intel nodes' btw. Foundries have followed a slightly different naming convention, where they go with half-nodes such as 28nm, 20nm and 14nm. Anyway, what really matters is probably gate-pitch and metal-pitch and not the channel length or the technology node name, really.Traditionally, foundries have offered tighter metal-pitches, because they were catering to high-density low-cost SoC customers, while Intel had more aggressive transistors and poly pitches, but relaxed metal pitches because they were going for higher performance laptop/desktop/server markets. Post 20nm, Intel and foundries have completely different definitions of the technology nodes....and the 'X nm' name does not mean anything real. For example, Intel's 14nm technology node has no feature that is exactly 14nm in dimension. And the same is true for Samsung's 14nm node. They have a certain gate-pitch and metal-pitch, which give us some indication of the actual density that you can get in the technology node. however, as lithography becomes more and more difficult, printing these features become tougher and the actual density suffers. Hence, it is completely possible that you can get denser and higher-performing chips using a more relaxed gate/metal pitch combination and not scaling as fast as your competition. All these things are considered when determining the next technology node by these fabs and hence the raw dimension numbers might not match our expectations. Also, it is completely incorrect to compare two technology nodes from different companies just based on a few dimensional parameters.
In short, it is completely true that Samsung's 14nm/10nm/7nm definition is unequal/different to Intel's. And so is TSMC's too...so all three foundries end up with different definitions and the only way to compare them is to look at power/performance/area/cost trends of taped-out chips.
Michael Bay - Friday, April 22, 2016 - link
>Samsung>eliminated the gap
>AMD being ahead of Intel in anything
Nice stuff, leave some for me.
medi03 - Sunday, April 24, 2016 - link
AMD APUs are way ahead of Intel at gaming.negusp - Sunday, May 8, 2016 - link
lol not anymore. The HD 520 is faster than pretty much all AMD offerings in their normal APUs and the Iris Graphics blow the rest to pot. In addition, quite a few games are CPU-limited and Intel is just so much faster.Yojimbo - Friday, April 22, 2016 - link
I don't think Samsung has clearly overtaken TSMC. From what I've read, Apple has chosen TSMC for its A9X and A10 SOCs because they are happier with TSMCs offerings than Samsung's.In addition, you can find analyses of the various processes about how Intel's 14nm has distinct advantages over TSMC's 16nm and Samsung's 14nm. AMD is not going to be ahead of Intel in process
Alexvrb - Friday, April 22, 2016 - link
Apple's preference for TSMC is heavily influenced by other factors. Samsung is a rather large influential competitor to Apple in the smartphone and tablet market. TSMC is not. As long as TSMC-produced chips are up to snuff they'll give preference to them. In the future TSMC may fall behind again (like when Samsung transitions to 10nm) and they may be forced to look elsewhere again (Samsung, GloFo) but right now they're doing well.name99 - Friday, April 22, 2016 - link
"Samsung has eliminated the gap completely, and clearly overtaken TSMC"Based on what? They have comparable performance today (The Apple A9 is the most obvious example of this), and their 10nm and 7nm roadmaps seem similar.
TSMC has not stated definitely that they will use EUV for 7nm, but has given dates (risk production in 2017, volume production in 2018), Samsung has said they will use EUV but has not given dates.
As for claiming that TSMC/Samsung's processes do not match their Intel equivalents, again in the A9 /A9Xwe have a test case. At comparable power budgets, Apple's chip gives comparable CPU performance and higher GPU performance in comparable silicon area. That's all that's required to say that the processes are comparable. Sure Intel wins in some areas (smaller transistors and metal features) but it loses in others (restricted layout rules compared to Samsung/TSMC). Practically this all appears to even out when all three processes are used by experts.
[Realistically, I think, you have to score Samsung and TSMC as coming out ahead by this metric. Intel's CPUs have been optimized over thirty year, and each new CPU has everything about it tightly matched to the precise Intel process. Apple has been in the business for a much shorter length of time, and is targeting two distinct processes --- so there is a limit to how much process-specific optimization they can engage in, and probably a lot more automatic rather than manual layout --- and yet they achieve similar performance...]
Arnulf - Friday, April 22, 2016 - link
"Based on what? They have comparable performance today (The Apple A9 is the most obvious example of this)"Yet TSMC chips are larger than those made by Samsung (by about 10%).
So to answer your question, based on process efficiency (density). Samsung can simply cram ~10% more transistors into same area, potentially leading to ~10% performance improvement (the benefit of which is easiest to manifest with highly-parallelized designs such as GPUs).
jasonelmore - Saturday, April 23, 2016 - link
Samsung's chips may be smaller but they run a lot hotter and while using the same amount of power as TSMC's. Heat= Leakage, in-efficient.milkod2001 - Monday, April 25, 2016 - link
This 7nm tech probably applies to small mobile chips only. If would be great but i don't think AMD will get access to any 7nm tech for their big desktop/server chips ahead of Intel anytime soon.JKflipflop98 - Tuesday, April 26, 2016 - link
As an electronics engineer that actually works in the industry, it's always funny reading the comments of the utterly clueless. Keep it up, anandtech commenters!psychobriggsy - Friday, April 22, 2016 - link
Regarding the defect density... if it was 0.2 per mm^2, then using http://www.isine.com/DieYieldCalculator.html we get for the ~10x10mm Apple A9 a yield of over 82%, which is pretty good for a fully working die.hellfish - Friday, April 22, 2016 - link
"While process technology might not be necessarily as interesting as the actual end product "Disagree, that's why we come here!
MarcHFR - Friday, April 22, 2016 - link
7nm EUV ? Samsung said"Low: Will EUV be ready at 7nm?
B. Suh: We are reviewing the possibility of EUV adoption very carefully and readiness for mass production will be determined accordingly."
So for me it's not sure at all
Anymoore - Friday, April 22, 2016 - link
Where to get the transcript?Anymoore - Friday, April 22, 2016 - link
Never mind, it's at the link.JoshHo - Friday, April 22, 2016 - link
The source was used for images and some general background but these statements were made in a separate briefing.Anymoore - Saturday, April 23, 2016 - link
Is there an official transcript of this briefing? Thanks.JoshHo - Saturday, April 23, 2016 - link
No such transcript exists.Krysto - Friday, April 22, 2016 - link
Sweetness. They must be using IBM's tech for 7nm. Now it's almost guaranteed Samsung will hit 7nm before Intel does.Krysto - Friday, April 22, 2016 - link
Also why can't Samsung buy AMD already? Imagine what powerful competition that could create for Intel? At least if Samsung was committed to designing chips. Right now I'm not convinced they are.lilmoe - Friday, April 22, 2016 - link
IKR...haukionkannel - Friday, April 22, 2016 - link
PC cpu is not atractive area to compete. Mobile cpu has better revenues and it is crovong market and PC is declining. Why invest in something that is not interesting. So there is not any reason for Samsung to buy AMD. Well the gpu part may be interesting, but AMD is not selling the only apartment that is making Profit for them.Murloc - Friday, April 22, 2016 - link
I guess that if they go bankrupt only the graphics part will survive.vladx - Saturday, April 23, 2016 - link
Samsung would have no interest in x86 tech, Apple on the other hand will keep selling Macs for years to go so they definitely wouldn't want to be at the hands of Intel.Michael Bay - Friday, April 22, 2016 - link
>IBM>litographic tech
>Samsung
>ahead of Intel
>guaranteed at that
IBM is nothing but a overmanaged slaughterhouse for its employees, trying to turn into outright patent troll. And Samsung always promises and never delivers.
I guess they make a good match.
jospoortvliet - Friday, April 22, 2016 - link
Samsung's been promising and (not) delivering a load of products... Mobile phones, memory, SSD's, heck my Microwave is Samsung ;-)Anymoore - Friday, April 22, 2016 - link
The triple patterning argument doesn't fly with me because they're using it for 10nm M1 layer.ingwe - Friday, April 22, 2016 - link
Hmm...my guess would be based on the fact that E-beam lithography takes twice as long (at minimum) to make a mask at 7 nm compared to 10 nm. So either double the time or double the cost compared to 10 nm and something has to give.Anymoore - Friday, April 22, 2016 - link
The mask for EUV would take exponentially longer since the features are actually smaller.Anymoore - Friday, April 22, 2016 - link
http://www.prnewswire.com/news-releases/mentor-gra..."The Olympus-SoC place and route platform is also certified for use at 10nm, with a comprehensive colored design methodology covering floorplanning, placement, extraction, routing and chip finishing requirements. To address the particular challenges of FinFET manufacturing, the platform supports M1 triple patterning, color shifting, non-uniform tracks, mask- and width-dependent spacing rules, and other new capabilities. Active deployment is underway at multiple mutual customers."
Triple patterning already qualified for Samsung 10nm M1.
jjj - Friday, April 22, 2016 - link
Where are they saying they'll use EUV? If anything they are saying that they won't. We are reviewing...... means yeah sure maybe at some point if it is ready and that's pretty much a no.Ryan Smith - Friday, April 22, 2016 - link
We had a call with Samsung on Thursday. They were rather explicit about intending to use EUV at 7nm (though obviously they still have challenges to resolve).Anymoore - Friday, April 22, 2016 - link
It's the same as saying, "we're stopping at 10nm, for now."watzupken - Saturday, April 23, 2016 - link
With news like this, I think Intel must be panicking. They used to have a good lead over the rest of the fabs, and thus, also gives their chips an edge in terms of performance vs power efficiency. With others catching up with them, that edge is gone and also making their effort to increase market shares vs ARM chips harder.Anymoore - Saturday, April 23, 2016 - link
In 2008, Intel published (link below) that EUV had a fundamental shot noise problem, so that dose would have to keep increasing with smaller size. So source power has to keepincreasing. That's the real reason EUV could never be implemented.http://ieuvi.org/TWG/Resist/2008/022808/simpleEUVS...
Krysto - Sunday, April 24, 2016 - link
So can we expect 10nm from Samsung in the first half of next year, and 7nm by the end of 2019?TC2 - Tuesday, May 3, 2016 - link
I just can't help myself :)Still there is funny peoples with their "AMD will, shall, could, ..."
AMD have nothing significant! They simply can wait someone to give them something :)
---
And now on the matter:
to have X nm process is one thing, to have ability to produce effectively large dies ... is completely different!
---
Live long & prosper !