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  • SaolDan - Wednesday, May 18, 2016 - link

    NEAT!!
  • Shadowmaster625 - Wednesday, May 18, 2016 - link

    So in about 3 years we will see products?
  • ddriver - Wednesday, May 18, 2016 - link

    Seems like 6 to 9 months to me
  • lefty2 - Wednesday, May 18, 2016 - link

    The first product will be the Apple A11 in autumn 2017.
  • revanchrist - Wednesday, May 18, 2016 - link

    If you meant the first 10nm Artemis SoC then it's probably MTK's Helio X30 which should be available on 1H 2017. But X30 has only two Artemis cores, so it's not really a high end product.
  • iwod - Wednesday, May 18, 2016 - link

    1H 2017, in small quantities and expensive, all the way until 1H 2018, in between you have Apple taking the majority of capacity.
  • levizx - Wednesday, August 17, 2016 - link

    Funny how Apple can also take capacity from GF/Samsung/Intel whilst having no chips with them.
  • Eden-K121D - Wednesday, May 18, 2016 - link

    will be interesting to see how Apple A11 and Snapdragon 830 perform as they will be made on 10nm FF process
  • Samus - Wednesday, May 18, 2016 - link

    It always is. Apple usually goes with 2 monster cores (with lots of cache) for strong single/dual threaded performance and others usually go for weaker quad or octa configs at higher frequencies and less cache per core. The optimization of iOS for single threaded performance often helps Apple boost performance too.
  • Sunamer - Wednesday, May 18, 2016 - link

    "The optimization of iOS for single threaded performance often helps Apple boost performance too."
    iOS is not single-thread optimized. Where did you get that from?
  • close - Thursday, May 19, 2016 - link

    Probably from the fact that Apple used almost exclusively 2 core implementations (with one 3 core exception) as opposed to the now common 4-8 core implementations used by others and maybe even the fact that Apple almost always leads the single threaded performance charts.

    Using a quarter of the cores to achieve similar performance and battery life suggests that they heavily optimize for single threaded operation.
  • schneeb - Wednesday, May 25, 2016 - link

    Those cores are often big/small not an actual quad core.
  • Flunk - Tuesday, May 24, 2016 - link

    I'm not an iOS expert but I was under the impression that the UI only runs on a single thread and secondary threads can only be used for background processing. Once again, I've only wrote a few iOS apps so it's possible this is out of date or incorrect.
  • jjj - Wednesday, May 18, 2016 - link

    So they push clocks up with Artemis and it's likely tiny on 10nm, tending towards half a mm2. They do need a bigger core , at the very least for 7nm given that TSMC is doing a process version for the server market.
    Interesting that in the power/perf slide they mention Artemis on 16ff+. Some gains from the architectural changes, some from higher clocks, should be nice since A72 is fast as it is.
  • JamieK - Wednesday, May 18, 2016 - link

    This is exciting that mobile and ARM are staying step by step with Intel on process improvements. I have read, often, though that the Intel and ARM gate sizes etc., mean that all 10nm chips aren't equally a 'real 10nm'.

    An in depth Anandtech comparison of the process technology comparisons at 16/10nm would be very interesting.

    A lot of it is marketing but they are genuinely new processes on smaller technology, the question is how small?

    Can anyone recommend such an article?
  • Andrei Frumusanu - Wednesday, May 18, 2016 - link

    So far I don't think TSMC has commented on actual dimensions other than saying 10FF is 2.1x denser than 16FF. It should be a solid die shrink according to that.
  • jjj - Wednesday, May 18, 2016 - link

    Anandtech can't do that comparison, they will never have access to that kind of data. A comparison is a lot more than just physical dimensions.There are design rules, there are costs ,it's a lot more complicated than just x or y nm. Smaller doesn't always mean better.
    You could look at this pdf ,page 17 and beyond but it's marketing so don't trust it too much http://files.shareholder.com/downloads/INTC/0x0x86...
    On slide 19 Intel's excuse for their lower density is that they use tall calls for a pretty large area - something that TSMC will be doing too with their 7nm HPC process version.
    The easiest comparison would be power,perf and cost for an ARM core and some SRAM for each foundry but unlikely we'll ever see that kind of data.
  • witeken - Wednesday, May 18, 2016 - link

    Summary: http://farm9.staticflickr.com/8125/15650137820_be3...
  • witeken - Wednesday, May 18, 2016 - link

    Also, 10nm of TSMC will be 0.53x the area of 16nm.
  • extide - Monday, May 23, 2016 - link

    Check out this image, it illustrates the differences between many of the process sizes: http://images.teraknor.net/Cell-SizeComparison-ful...
  • tipoo - Wednesday, May 25, 2016 - link

    Was just going to post this. When any other fab says they're on the same size as Intel, I assume it's closer to Intels n-1 generation.
  • boozed - Wednesday, May 18, 2016 - link

    What do the pretty colours on the chip layouts mean?
  • videogames101 - Wednesday, May 18, 2016 - link

    They represent various "modules" within the HDL code that the layout was generated from. "Modules" are logical constructs used to separate functionality within the core.
  • bobj3832 - Thursday, May 19, 2016 - link

    Yep. It looks like the screenshots are from Cadence SOC Encounter (now renamed Innovus)

    I run this thing everyday to do physical design for integrated circuits.

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